Join Google's custom silicon team to develop high-performance hardware for consumer products. Define microarchitecture, implement RTL using Verilog/SystemVerilog, and optimize subsystems for power, performance, and area. Lead engineering teams to deliver high-quality designs while performing critical quality checks and ensuring seamless integration across complex hardware systems.

Join the ASIC design team as an IR and EM Technology Expert. You will develop solutions for signal and power integrity, thermal management, and ASIC performance optimization. This role involves creating models, scripts, and tools while performing complex simulations to ensure design compliance and reliability in cutting-edge semiconductor solutions.

Join NVIDIA’s Digital IP group as a Senior SRAM Circuit Design Engineer. You will design transistor-level embedded SRAM macros, develop sophisticated compilers, and optimize power, performance, and area for advanced process nodes. This high-visibility role involves guiding SOC design and silicon testing to deliver world-class IP for revolutionary products.

Drive TPU technology innovation by designing and deploying ASIC projects through emulation-based prototyping. You will build complex SoC prototypes, develop system-level models, and execute full-chip tests on industry-standard platforms. This role focuses on verifying digital designs to power the future of AI and machine learning hardware acceleration.

Join a global semiconductor leader as a Staff Digital Design Engineer. You will develop digital controllers for next-generation power management products, creating micro-architectures and RTL code. This role involves designing performance enhancement algorithms for analog circuits and ensuring seamless integration from RTL to GDSII within mixed-signal environments.

Join NVIDIA as a Senior SRAM Circuit Design Engineer to develop cutting-edge memory arrays for high-performance CPUs and GPUs. You will design transistor-level circuits, optimize for power and area, and utilize advanced technology nodes like 7nm. This role involves spice verification, schematic entry, and creating automated design flows.

Join Google Cloud to develop custom silicon solutions powering AI/ML hardware acceleration. You will drive TPU technology innovation through SoC design, implementation, and integration. This role involves RTL coding, performance simulation, and verification of complex digital designs to deliver high-performance hardware experiences for millions of users worldwide.

Join Infineon as a Staff Digital Design Engineer focusing on RTL design and IO pad integration. You will develop highly configurable IO subsystems, manage multiplexing logic, and integrate power control signals. This role requires expertise in ASIC design flows, Verilog, and automation to drive semiconductor innovation in IoT and power systems.