Join Google Cloud to develop custom silicon solutions powering AI/ML hardware acceleration. You will drive TPU technology innovation through SoC design, implementation, and integration. This role involves RTL coding, performance simulation, and verification of complex digital designs to deliver high-performance hardware experiences for millions of users worldwide.

Join the ASIC design team as an IR and EM Technology Expert. You will develop solutions for signal and power integrity, thermal management, and ASIC performance optimization. This role involves creating models, scripts, and tools while performing complex simulations to ensure design compliance and reliability in cutting-edge semiconductor solutions.

Join Meta's Infra Silicon team to design high-performance hardware accelerator ASICs. You will drive architecture exploration, micro-architecture development, and RTL coding for domain-specific SoCs. This role focuses on optimizing data center efficiency for AI/ML and video workloads through advanced silicon design, synthesis, and power optimization techniques.

Join NVIDIA as a Senior Circuit Design Engineer to develop groundbreaking IPs for GPUs, CPUs, and networking chips. You will architect innovative circuit solutions, perform SPICE simulations, and improve silicon correlation. This role involves mentoring junior members and leveraging AI/ML tools to optimize chip performance and power efficiency.

Join Amazon Lab126 as a Senior RTL Design Engineer to define micro-architecture and implement RTL for advanced functional blocks. You will drive the design, verification, and bring-up of complex hardware for consumer electronics. This role involves developing detailed specifications, performing synthesis, and ensuring high-quality silicon production for world-class devices.

Develop custom silicon solutions powering Google's consumer products. You will own System Verilog implementation, lead PPA optimization experiments, and drive RTL coding. This role involves defining block-level designs, performing simulation debugging, and managing timing closure to deliver high-performance hardware experiences for millions of users worldwide.

Join a global semiconductor leader as a Staff Digital Design Engineer. You will develop digital controllers for next-generation power management products, creating micro-architectures and RTL code. This role involves designing performance enhancement algorithms for analog circuits and ensuring seamless integration from RTL to GDSII within mixed-signal environments.

Join NVIDIA’s Digital IP group as a Senior SRAM Circuit Design Engineer. You will develop sophisticated SRAM compilers and embedded macros using advanced FinFET processes. Responsibilities include transistor-level design, layout supervision, and performance optimization. Help shape future process nodes and drive silicon productization for world-changing AI and graphics technologies.